1. Field of the Invention
The present invention generally relates to a process for manufacturing semiconductor transistors and more particularly to an improved process for simultaneously forming N-type and P-type transistor gates on an integrated chip substrate.
2. Description of the Related Art
As the technologies surrounding integrated circuit chips progress, numerous advances have been made to reduce the size of transistors as well as to simplify the manufacturing process. Generally, such advances strive to reduce the size and cost of the integrated circuit chip while increasing the operating speed of the chip. In addition, it is important to simplify the manufacturing process so as to reduce the amount of time required to manufacture integrated circuit chips and to increase the yield of the manufacturing process.
One recent advance in complementary metal oxide semiconductor (CMOS) manufacturing processes that increases the device""s speed, makes it necessary to simultaneously form N and P doped transistors gates on a single integrated circuit substrate. By simultaneously forming these different types of transistors, the number of steps in the manufacturing process is reduced, which makes the manufacturing process faster and less-expensive.
One example (which is not necessarily prior art) of this processing is shown in FIGS. 1 and 2. More specifically, FIG. 1 illustrates a semiconductor chip that includes a substrate 10 (for example, silicon), well regions 17 (N and P type, respectively), a gate oxide layer 18 and a conductor layer over the gate oxide layer 18. The conductor layer, typically a semiconductor material such as polysilicon, includes differently doped regions including a N-type region 12 and a P-type region 14. The polysilicon layer is selectively doped with N and P type dopants in different parts of the chip by ion implant using a patterned mask.
In addition, FIG. 1 illustrates a patterned mask 16, typically a hard mask of material such as nitride, TEOS, thermal oxide, or the like, that is used to pattern the conductor layer 12, 14 into gate conductors. Conventionally, a plasma etch process is used in conjunction with the mask 16 to remove portions of the conductor 12, 14 that are not protected by the mask. This processing produces N-type and P-type gate conductors 20 and 22, respectively. Subsequently, impurities are implanted into the substrate (preferably using the mask 16 to self-align these implants) to form source/drain regions 24. The gate conductors are doped separately from the source/drain regions 24 because different impurities are used in the gate conductors and in the source/drain regions 24. In early generation N devices, the gate conductor 20 and source/drain 24 were both doped with arsenic. In current generation devices, it is now preferable to dope the N gate conductor 20 with phosphorus first and subsequently dope the source/drain 24 with arsenic after the formation of the gate conductor 20. The P dopant in the gate makes for a faster operating device. By contrast, P devices are typically doped differently than N devices, for example, by doping the gate conductor 22 with boron ions and then doping the source/drain with BF2 ions after the formation of the gate conductor 22.
Improved processing attempts to integrate process steps to simultaneously form N-type and P-type gate structures. For example, such processing dopes different regions of the conductor layer using an ion implant method that localizes doping in a region within the conductor layer, followed by an annealing step to spread the dopant. The annealing process can occur before or after the formation of the gate stack by patterned etching with the hard mask 16. In this integration scheme, it is necessary to pattern the gate structures containing both N-doped poly and P-doped poly. The challenge is similar to that with N and P doped gates. However, a problem exists in that the impurity used for the N-type gate conductor 20 causes the N-type gate conductor 20 to suffer substantially more erosion during the plasma etch process when compared to the P-type gate conductors 22. This is schematically demonstrated in FIG. 2 where the N-type gate conductor 20 is shown to have excessive etching when compared to the P-type gate conductor 22. The performance of such a device will suffer because of the erosion to the critical dimension (CD) and gate profile.
Conventional processing can result in vertical P-type gate profiles, but cause differential lateral etching of the N-doped regions. Aggressive anisotropic etching minimizes such differentials; however, such aggressive anisotropic etching may cause damage to the gate oxide. The alternative of processing N-type and P-type structures separately is more costly. The invention described below provides an integrated processing scheme that allows the formation both N-type and P-type structures that have the desired vertical profiles and critical dimensions without significant additional cost or complexity to the processing. An alternative to the foregoing process involves etching the N-type gate conductors separately from the P-type gate conductors. However, this alternative requires additional masking and etching steps because one type of gate conductor must be protected during the etching of the other gate conductor and vice versa. Therefore, this alternative is not attractive because it adds additional manufacturing steps, which increases the cost and time needed to manufacture an integrated circuit chip. In addition, this processing may introduce additional impurities which reduce yield. It is also important to be able to obtain same profile and critical dimensions for the gate of N doped, P doped, and undoped devices, which is difficult to achieve with conventional methods.
Therefore, there is a need to improve the manufacturing process that simultaneously etches differently doped conductors, without resulting in excessive erosion of the N-type gate conductors. The invention described below provides a solution that adds a minimum number of processing steps, yet achieves the goal of producing substantially equivalently shaped N-type and P-type gate conductors in a simultaneous etching process.
It is therefore, an object of the present invention to provide a method for manufacturing a semiconductor chip which has transistors. The transistors include first type transistors which have a first type (e.g., P-type) of doping and second type transistors which have a second type (e.g., N-type) of doping that is different than the first type of doping. The method forms a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions that have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer, such that a layer of the unprotected portions remain. The substrate is not exposed by the partially etching process. The invention forms a passivating layer on exposed vertical surfaces of the conductive layer and completely etches unprotected portions of the conductive layer to expose the substrate. The invention then dopes exposed portions of the substrate to form source/drain regions 24.
The conductive layer includes a lower layer of undoped polysilicon, a middle layer of doped polysilicon, and an upper layer of undoped polysilicon. The partially etching process etches the unprotected portions of the conductive layer through the upper layer and the middle layer, and partially through the lower layer. The passivating layer is formed at least over vertical surfaces of the middle layer. The passivating layer is formed upon the vertical surfaces and on horizontal surfaces of the conductive layer and then removed from the horizontal surfaces. The forming of the passivating layer can also include oxidizing the vertical surfaces, nitridizing the vertical surfaces, depositing a nitride material, depositing an oxide material on the vertical surfaces, or polymerizing the conductive layer. The passivating layer protects sidewall portions of the conductive layer from lateral etching during the subsequent etching.
The invention solves the conventional over-etching problems by a sequence of steps that include first etching the gate into a depth just beyond the region of the dopant (before annealing and when the dopant is localized within a small depth region). Aggressive etching is performed so that lateral etching of the region containing the dopant is minimized. The next step is to form a passivation layer on the vertical surfaces of the partially formed gate structures of both N doped and P doped (or undoped ) devices. Note that the passivation would occur on the horizontal surfaces at the same time as well. Further processing utilizes a less aggressive plasma etching to remove the remaining polysilicon layer (now that the doped region is protected, the less aggressive etching process is used to avoid damaging the oxide layer). The passivating layer prevents the N-type doped region of the gate conductor from suffering the excessive sidewall etching that is seen in the conventional processes.